J3-L1-忆月启函

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J3-L1

Function Description

Strong platform expansion

32bit CPU architecture, good ecological environment

Rich peripheral resources to meet the platform expansion

Ultra-high reliability

ISO26262 and AEC-Q100 Grade 1 certification

Support -40°C to 125°C

15-year design life, >15 years supply chain guarantee

High-cost performance

Equal performance/resources for higher cost performance

Quality service

Complete ecological support and Turnkey solution

Product performance

System resource

•32bit CPU •Support for 32bit single-period multipliers •Support 256KBs Embedded Flash (ECC) •Support 32KBs SRAM (ECC)

Peripheral resources

•1 channel CAN-FD, compatible with CAN 2.0B •2-channel UART, and 1 channel supports UART LIN multiplexing •2-channel SPI supports master-slave mode •1 channel I2C supports the master-slave mode •1 channel hardware LIN bus •2 x 8-channel complementary pulse-width modulation (PWM) timers •1 x 4-channel periodic interrupt timer •2 Pulse Width Timer (PWDT) •1 real-time clock (RTC)

Simulation

•1 x 12bit ADC, 1Msps, supporting 16 channels •1 x 8bit DAC •2 x analog comparator with built-in 8bit DAC •4 x operational amplifier •1 x temperature sensor, ±0.5℃

Package

•QFN 32 ( 5mmx5mm ) •LQFP 48 ( 7mmx7mm ) •LQFP 64 ( 10mmx10mm )

System Block Diagram